- Published on
Building the Hack Computer with 74HC Logic A Comprehensive Tutorial
- Authors
- Name
- Yinhuan Yuan
Building the Hack Computer with 74HC Logic: A Comprehensive Tutorial
I'll create a detailed guide for implementing the Hack machine from Nand2Tetris using 74HC logic ICs. This is an ambitious project that will give you deep insight into computer architecture!
Table of Contents
- Architecture Overview
- Component Selection & Bill of Materials
- ALU Design
- Register File Design
- Control Unit Design
- Memory Interface
- Integration & Testing
- PCB Design Considerations
1. Architecture Overview
Hack Computer Specifications
- 16-bit data bus
- 15-bit address bus (32K addressable memory)
- Harvard architecture (separate instruction/data paths)
- Three registers: A (address/data), D (data), PC (program counter)
- Simple instruction set: A-instructions and C-instructions
Block Diagram
┌─────────────────────────────────────────────────────────┐
│ HACK COMPUTER │
├──────────────┬──────────────┬──────────────┬────────────┤
│ CPU │ INST ROM │ DATA RAM │ I/O │
│ │ (32K x 16) │ (32K x 16) │ │
│ ┌────────┐ │ │ │ Screen │
│ │ ALU │ │ │ │ Keyboard │
│ ├────────┤ │ │ │ │
│ │A-Reg(16)│ │ │ │ │
│ │D-Reg(16)│ │ │ │ │
│ │PC (15) │ │ │ │ │
│ └────────┘ │ │ │ │
└──────────────┴──────────────┴──────────────┴────────────┘
2. Component Selection & Bill of Materials
Core Logic ICs
Registers & Storage
- 74HC574 (×8): Octal D flip-flop, 3-state (for A and D registers)
- 74HC161 (×4): 4-bit synchronous counter (for PC)
- 74HC273 (×2): Octal D flip-flop (for control signals)
ALU Components
- 74HC283 (×4): 4-bit binary full adder
- 74HC86 (×4): Quad 2-input XOR gate
- 74HC32 (×4): Quad 2-input OR gate
- 74HC08 (×4): Quad 2-input AND gate
- 74HC04 (×4): Hex inverter
Multiplexers & Demux
- 74HC157 (×8): Quad 2-input multiplexer
- 74HC151 (×4): 8-input multiplexer
- 74HC138 (×2): 3-to-8 decoder
Memory
- AS6C4008 (×2): 512K×8 SRAM (for data RAM)
- AT28C256 (×2): 32K×8 EEPROM (for instruction ROM)
- 74HC245 (×4): Octal bus transceiver (for bus isolation)
Clock & Control
- 74HC00 (×2): Quad NAND gate
- 74HC02 (×2): Quad NOR gate
- 74HC74 (×2): Dual D flip-flop
- 555 timer (×1): Clock generation
- Crystal oscillator or adjustable clock
Misc
- 74HC688 (×2): 8-bit comparator
- 74HC125 (×4): Quad bus buffer, 3-state
- Resistor networks, capacitors, LEDs for debugging
3. ALU Design (Arithmetic Logic Unit)
The Hack ALU performs 18 functions based on 6 control bits: zx, nx, zy, ny, f, no
ALU Control Signals
zx: zero the x input
nx: negate the x input
zy: zero the y input
ny: negate the y input
f: function select (1=add, 0=and)
no: negate the output
ALU Circuit Design (16-bit, divided into 4×4-bit slices)
Stage 1: X Input Conditioning (×4 for 16 bits)
For each 4-bit slice:
X[3:0] ──┬──[74HC157 MUX]── X_zeroed[3:0] ──[74HC86 XOR]── X_processed[3:0]
│ (zx select) (nx control)
0000─┘
Components per slice:
- 1× 74HC157 (quad 2:1 mux) for zero selection
- 1× 74HC86 (quad XOR) for negation
Stage 2: Y Input Conditioning (identical to X)
Y[3:0] ──┬──[74HC157 MUX]── Y_zeroed[3:0] ──[74HC86 XOR]── Y_processed[3:0]
│ (zy select) (ny control)
0000─┘
Stage 3: Function Execution (ADD or AND)
For each 4-bit slice:
X_processed[3:0] ─┬─[74HC283 ADDER]─ SUM[3:0]
│
Y_processed[3:0] ─┤
│
└─[74HC08 AND]──── AND[3:0]
[74HC157 MUX]──── F_out[3:0]
(f select)
Components per slice:
- 1× 74HC283 (4-bit adder with carry)
- 1× 74HC08 (quad AND gate)
- 1× 74HC157 (quad 2:1 mux) for function select
Stage 4: Output Negation
F_out[3:0] ──[74HC86 XOR]── ALU_out[3:0]
(no control)
Stage 5: Status Flags
Zero Flag (zr):
ALU_out[15:0] ──[74HC4078 8-input NOR]×2── [74HC02 NOR]── zr
(combine)
Negative Flag (ng):
ALU_out[15] ────────────────────────────────────────────── ng
Complete ALU Schematic (One 4-bit Slice)
X[3:0] Y[3:0]
│ │
├─────────┐ ├─────────┐
│ │ │ │
┌───▼───┐ ┌───▼───┐ ┌──▼────┐ ┌──▼────┐
│74HC157│ │74HC157│ │74HC157│ │74HC157│
│ MUX │ │ MUX │ │ MUX │ │ MUX │
│zx sel │ │zx sel │ │zy sel │ │zy sel │
└───┬───┘ └───┬───┘ └───┬───┘ └───┬───┘
│ │ │ │
┌───▼───┐ ┌───▼───┐ ┌───▼───┐ ┌───▼───┐
│74HC86 │ │74HC86 │ │74HC86 │ │74HC86 │
│ XOR │ │ XOR │ │ XOR │ │ XOR │
│nx ctl │ │nx ctl │ │ny ctl │ │ny ctl │
└───┬───┘ └───┬───┘ └───┬───┘ └───┬───┘
│ │ │ │
X_proc[1:0] X_proc[3:2] Y_proc[1:0] Y_proc[3:2]
│ │ │ │
├─────────┼─────────┼─────────┤
│ │ │ │
┌──▼─────────▼──┐ ┌──▼─────────▼──┐
│ 74HC283 │ │ 74HC08 │
│ 4-bit ADD │ │ 4-bit AND │
└───────┬───────┘ └───────┬───────┘
│ │
SUM[3:0] AND[3:0]
│ │
└────┬──────────────┘
│
┌───▼────┐
│74HC157 │
│ MUX │
│ f sel │
└───┬────┘
│
F_out[3:0]
│
┌───▼────┐
│74HC86 │
│ XOR │
│ no ctl │
└───┬────┘
│
ALU_out[3:0]
Repeat this circuit 4 times for all 16 bits!
4. Register File Design
A Register (16-bit Address/Data Register)
Circuit using 74HC574 (Octal D flip-flop with 3-state output):
Data_In[15:0]
│
┌─────────┼─────────┐
│ │ │
┌─▼───────┐ │ ┌───────▼─┐
│ 74HC574 │ │ │ 74HC574 │
│ [7:0] │ │ │ [15:8] │
└─┬───────┘ │ └───────┬─┘
│ CLK◄──┼─────────┤
│ /OE │ │
└─────────┼─────────┘
│
A_Reg[15:0]
Control signals:
- CLK: Load signal (write enable)
- /OE: Output enable (active low)
Total ICs: 2× 74HC574
D Register (16-bit Data Register)
Identical to A register:
Total ICs: 2× 74HC574
Program Counter (15-bit)
Uses 74HC161 (4-bit synchronous counter) for auto-increment functionality.
Circuit for PC:
┌──────────┐ ┌──────────┐ ┌──────────┐ ┌──────────┐
│ 74HC161 │ │ 74HC161 │ │ 74HC161 │ │ 74HC161 │
│ [3:0] │ │ [7:4] │ │ [11:8] │ │ [14:12] │
│ │ │ │ │ │ │ (+GND) │
│ TC───┼─►│CLK EN │ │ │ │ │
│ │ │ TC───┼─►│CLK EN │ │ │
│ │ │ │ │ TC───┼─►│CLK EN │
└──────────┘ └──────────┘ └──────────┘ └──────────┘
▲ ▲ ▲ ▲
│ │ │ │
┌────┴─────────────┴─────────────┴─────────────┴────┐
│ Parallel Load (from A register) │
└────────────────────────────────────────────────────┘
Control signals:
- CLK: System clock
- LOAD: Parallel load enable (jump)
- INC: Increment enable
- RESET: Asynchronous reset
Total ICs: 4× 74HC161
Special PC control logic:
Using 74HC00 (NAND gates) and 74HC02 (NOR gates):
PC_LOAD = JUMP_CONDITION (from control unit)
PC_INC = /JUMP_CONDITION AND /RESET
This ensures PC increments unless jumping or reset.
5. Control Unit Design
The control unit decodes instructions and generates all control signals.
Instruction Decode
A-Instruction (bit 15 = 0):
Format: 0vvvvvvvvvvvvvvv
Action: Load value into A register
C-Instruction (bit 15 = 1):
Format: 111a cccc ccdd djjj
a: A/M select (0=A, 1=M)
cccccc: ALU control (zx,nx,zy,ny,f,no)
ddd: Destination (A,D,M)
jjj: Jump condition
Control Signal Decoder
Instruction[15:0] from ROM
│
├──[Bit 15]────► INST_TYPE (0=A-inst, 1=C-inst)
│
├──[14:13]─────► unused in Hack (ignore)
│
├──[12]────────► A_or_M (ALU Y input: 0=A, 1=M[A])
│
├──[11:6]──────► ALU_CTRL[5:0] (zx,nx,zy,ny,f,no)
│
├──[5:3]───────► DEST[2:0] (destA, destD, destM)
│
└──[2:0]───────► JUMP[2:0] (jjj codes)
Using 74HC138 decoders and 74HC00/74HC02 logic gates:
DEST Decoder:
Bit[5] ──► destA (write to A)
Bit[4] ──► destD (write to D)
Bit[3] ──► destM (write to RAM)
JUMP Logic (74HC151 8:1 MUX + comparators):
Input: JUMP[2:0], ALU_ng, ALU_zr
Output: PC_LOAD (jump taken)
Truth table:
jjj | Condition | Jump if
----|-----------|----------
000 | null | never
001 | JGT | !zr AND !ng
010 | JEQ | zr
011 | JGE | !ng
100 | JLT | ng
101 | JNE | !zr
110 | JLE | zr OR ng
111 | JMP | always
Control Signal Summary
Generate these signals from instruction decoder:
1. LOAD_A: Load A register (A-instruction OR destA)
2. LOAD_D: Load D register (destD AND C-instruction)
3. WRITE_M: Write to RAM (destM AND C-instruction)
4. PC_INC: Increment PC
5. PC_LOAD: Load PC (jump taken)
6. ALU_CTRL[5:0]: ALU operation
7. A_OR_M: Select A or M[A] for ALU input
Circuit using 74HC logic:
┌─────────────────────────────────────┐
│ Instruction Decoder │
│ │
│ Inst[15] ──[74HC04]──► /C_INST │
│ Inst[12] ────────────► A_OR_M │
│ Inst[11:6] ──────────► ALU_CTRL │
│ │
│ ┌──────────────────┐ │
│ │ DEST Decode │ │
│ │ (74HC08/74HC32) │ │
│ ├──────────────────┤ │
│ │ Inst[5] ─► destA │──► LOAD_A │
│ │ Inst[4] ─► destD │──► LOAD_D │
│ │ Inst[3] ─► destM │──► WRITE_M │
│ └──────────────────┘ │
│ │
│ ┌──────────────────┐ │
│ │ JUMP Logic │ │
│ │ (74HC151 MUX) │ │
│ ├──────────────────┤ │
│ │ Inst[2:0]─┬──►SEL│ │
│ │ ALU_zr ───┤ │ │
│ │ ALU_ng ───┴─►DATA│──► PC_LOAD │
│ └──────────────────┘ │
└─────────────────────────────────────┘
6. Memory Interface
ROM (Instruction Memory)
Using AT28C256 EEPROM (32K×8):
┌──────────────────┐ ┌──────────────────┐
│ AT28C256 (Lo) │ │ AT28C256 (Hi) │
│ [7:0] │ │ [15:8] │
└──────────────────┘ └──────────────────┘
▲ ▲
│ │
Address[14:0] from PC
/OE = GND (always reading)
/CE = GND (always enabled)
Total: 2× AT28C256 for 16-bit instructions
RAM (Data Memory)
Using AS6C4008 SRAM (512K×8):
┌──────────────────┐ ┌──────────────────┐
│ AS6C4008 (Lo) │ │ AS6C4008 (Hi) │
│ [7:0] │ │ [15:8] │
└──────────────────┘ └──────────────────┘
▲ ▲
│ │
Address[14:0] from A register
/OE = /READ_M (active during read)
/WE = /WRITE_M (active during write)
/CE = GND (always enabled)
Total: 2× AS6C4008
Bus Switching
Use 74HC245 bus transceivers to manage data flow:
CPU Data Bus [15:0]
│
┌─────────┼─────────┐
│ │ │
┌─▼────┐ ┌─▼────┐ ┌─▼────┐
│74HC245 │74HC245 │74HC245│
│ ROM │ │ RAM │ │ ALU │
│interface│ │interface│ │out │
└────────┘ └────────┘ └──────┘
DIR signals control data flow direction
/OE signals enable specific buses
7. Clock and Timing
Clock Generator
Simple adjustable clock using 555 timer:
+5V
│
├──────┬───────┐
R1 │ │
│ │ ┌┴┐
├──────┤4 8 │ │
│ │ │C│ 0.1µF
R2 ┌─┴──┐ │ │
│ │555 │ └┬┘
┌┴┐ │ │ │
│ │ │ │3───┼──► CLK_OUT
│C│ │ │ │
└┬┘ └────┘ │
│ │ │
GND GND GND
R1 = 1KΩ
R2 = 10KΩ potentiometer (adjustable frequency)
C = 10µF (adjust for desired frequency)
Frequency ≈ 1.44 / ((R1 + 2×R2) × C)
For debugging: ~1Hz to 10Hz
For running: 1MHz to 4MHz
Clock Distribution
Use 74HC04 hex inverter as clock buffer:
555_OUT ──[74HC04 buffer]──┬─► to all registers
├─► to PC
├─► to control unit
└─► to memory
Multi-Phase Clock (if needed)
For more complex timing:
CLK ──[74HC74 D-FF]──► CLK_delayed
(divide by 2)
This creates φ1 and φ2 clock phases
8. Complete System Integration
Pin Count Summary (approximate)
- 74HC574 registers: 10 ICs (A, D registers)
- 74HC161 counters: 4 ICs (PC)
- 74HC283 adders: 4 ICs (ALU)
- 74HC86 XOR gates: 12 ICs (ALU conditioning & negation)
- 74HC157 muxes: 16 ICs (ALU paths)
- 74HC08 AND gates: 4 ICs (ALU)
- 74HC245 transceivers: 4 ICs (bus control)
- Control logic: ~10 ICs (decoders, gates)
- Memory: 4 ICs (2× ROM, 2× RAM)
Total: ~70-80 ICs
Power Distribution
Requirements:
- Voltage: +5V ±5%
- Current: ~2A (depending on clock speed)
- Decoupling: 0.1µF ceramic cap per IC
- Bulk: 10µF electrolytic every 10 ICs
Power plane design:
┌────────────────────────────────┐
│ +5V Power Supply (regulated) │
│ (7805 or switching regulator) │
└─────────┬──────────────────────┘
│
┌─────┴─────┐
│ Power │
│ Planes │
│ (PCB) │
└───────────┘
PCB Layout Recommendations
Layer Stack:
- Top: Signal + Components
- Layer 2: Ground plane
- Layer 3: Power plane (+5V)
- Bottom: Signal + Components
Design Guidelines:
- Keep clock traces short (<3 inches)
- Use ground plane for return paths
- Star grounding for analog/digital separation
- Bypass caps close to IC power pins
- Bus routing: group data/address lines
- Minimum trace width: 10 mil
- Minimum clearance: 10 mil
Module Layout Suggestion
┌────────────────────────────────────────────┐
│ [Power Supply] [Clock] [Reset] │
├────────────────────────────────────────────┤
│ │
│ ┌──────────┐ ┌──────────┐ ┌──────────┐ │
│ │ ROM │ │ RAM │ │ BUS │ │
│ │ (2 ICs) │ │ (2 ICs) │ │Interface │ │
│ └──────────┘ └──────────┘ └──────────┘ │
│ │
│ ┌──────────────────────────────────────┐ │
│ │ ALU (20+ ICs) │ │
│ │ [Input Cond.][ADD/AND][Output Neg.] │ │
│ └──────────────────────────────────────┘ │
│ │
│ ┌──────────┐ ┌──────────┐ ┌──────────┐ │
│ │ A Reg │ │ D Reg │ │ PC │ │
│ │ (2 ICs) │ │ (2 ICs) │ │ (4 ICs) │ │
│ └──────────┘ └──────────┘ └──────────┘ │
│ │
│ ┌──────────────────────────────────────┐ │
│ │ Control Unit (10+ ICs) │ │
│ │ [Decoder][DEST][JUMP][Clock Logic] │ │
│ └──────────────────────────────────────┘ │
│ │
│ [LED Indicators] [Debug Headers] │
└────────────────────────────────────────────┘
Board size estimate: 12" × 10"
9. Testing Strategy
Phase 1: Power-On Test
- Apply power, check voltage rails
- Verify clock signal
- Test reset functionality
Phase 2: Module Testing
Order of testing:
1. Clock generation ✓
2. Register loading (A, D, PC) ✓
3. ALU operations ✓
4. Control signal generation ✓
5. Memory read/write ✓
6. Instruction fetch ✓
7. Full instruction execution ✓
Phase 3: Program Testing
Load simple test programs:
// Test 1: Load constant to A
@5
D=A
// Test 2: Simple arithmetic
@3
D=A
@2
D=D+A // D should be 5
// Test 3: Memory write/read
@16
M=D // Write to RAM[16]
D=M // Read back
// Test 4: Conditional jump
@0
D=M
@END
D;JGT // Jump if D > 0
@END
0;JMP
Debug Tools
Add these to your design:
1. LED indicators:
- ALU output [15:0]
- Register values (selectable via switches)
- Control signals
- PC value
2. Logic analyzer connection points:
- All major buses
- Control signals
- Clock
3. Single-step mode:
- Manual clock button
- Clock halt switch
4. Display module:
- 7-segment displays for key values
- LCD for instruction disassembly
10. Advanced Enhancements
Speed Optimization
- Use 74HCT for better noise immunity
- Add pipeline registers
- Upgrade to 74AC series (faster)
I/O Extensions
- Add UART for serial communication
- VGA output for screen
- PS/2 keyboard interface
- SD card for program loading
Debugging Features
┌─────────────────────────────────┐
│ Debug Module │
├─────────────────────────────────┤
│ • Breakpoint comparators │
│ • Single-step logic │
│ • Register dump functionality │
│ • Memory inspector │
│ • Trace buffer (74HC670 FIFO) │
└─────────────────────────────────┘
11. Programming the ROM
Use a ROM programmer to load Hack machine code:
# Python script to generate ROM images
def hack_to_hex(hack_asm):
# Parse .hack file
# Convert 16-bit binary to hex
# Split into low/high bytes
# Generate two .hex files for ROM programmer
pass
# Example ROM image format (Intel HEX):
:10000000XXXXXXXXXXXX...XX
12. Estimated Costs
- 74HC ICs: ~$80-120 (bulk purchase)
- Memory chips: ~$20-30
- PCB fabrication: ~$50-100 (4-layer)
- Components (caps, resistors, etc.): ~$30
- Connectors, sockets: ~$40
- Power supply: ~$20
Total: ~$250-350
13. Alternative Simplified Approach
If 80+ ICs is too daunting, consider:
Option A: Use larger scale integration
- Replace ALU with AMD Am2901 bitslice processor
- Use 74HC670 register files instead of discrete registers
- Reduces to ~30 ICs
Option B: Hybrid approach
- Use CPLD/FPGA for control logic only
- Keep datapath in discrete 74HC
- Best of both worlds for learning
Option C: Modular build
Build one section at a time:
- Week 1-2: ALU module
- Week 3: Register file
- Week 4: Control unit
- Week 5: Integration
- Week 6: Testing & debugging
Resources & References
Datasheets needed:
- 74HC series logic families
- Memory chips (SRAM/EEPROM)
- Bus transceivers
Tools:
- KiCad or Eagle (PCB design)
- Logic analyzer
- Oscilloscope
- ROM programmer
Similar projects:
- Ben Eater's 8-bit computer (excellent reference)
- Magic-1 homebrew computer
- Nand2Tetris forums
This is a massive but incredibly rewarding project! Would you like me to elaborate on any specific section, such as detailed PCB layouts, specific IC pinouts, or testing procedures?
Detailed PCB Layouts and IC Pinouts for Hack Computer
I'll provide comprehensive PCB design information with actual pin connections.
Table of Contents
- IC Pinout Reference
- ALU Module PCB Layout
- Register File PCB Layout
- Control Unit PCB Layout
- Memory Module PCB Layout
- Main Board Integration
- Critical Routing Guidelines
1. IC Pinout Reference
74HC574 - Octal D-Type Flip-Flop (for A & D Registers)
74HC574
┌──┴──┐
/OE │1 20│ VCC
D0 │2 19│ D7
D1 │3 18│ D6
D2 │4 17│ D5
D3 │5 16│ D4
Q0 │6 15│ Q7
Q1 │7 14│ Q6
Q2 │8 13│ Q5
Q3 │9 12│ Q4
GND │10 11│ CLK
└─────┘
Pin Assignments:
- Pin 1: /OE (Output Enable, active LOW)
- Pins 2-5: Data inputs D0-D3
- Pins 6-9: Data outputs Q0-Q3
- Pin 10: GND
- Pin 11: CLK (Clock input)
- Pin 12-15: Data outputs Q4-Q7
- Pin 16-19: Data inputs D4-D7
- Pin 20: VCC (+5V)
Critical:
- Add 0.1µF cap between pins 20-10
- Keep CLK trace < 2 inches
- /OE can be tied to GND for always-on
74HC161 - 4-bit Synchronous Counter (for Program Counter)
74HC161
┌──┴──┐
/CLR │1 16│ VCC
CLK │2 15│ RCO (Ripple Carry Out)
A │3 14│ QA
B │4 13│ QB
C │5 12│ QC
D │6 11│ QD
ENP │7 10│ ENT
GND │8 9│ /LOAD
└─────┘
Pin Assignments:
- Pin 1: /CLR (Clear, active LOW)
- Pin 2: CLK (Clock)
- Pins 3-6: Parallel load inputs A-D
- Pin 7: ENP (Enable P - must be HIGH to count)
- Pin 8: GND
- Pin 9: /LOAD (Load, active LOW)
- Pin 10: ENT (Enable T - must be HIGH to count)
- Pins 11-14: Outputs QA-QD
- Pin 15: RCO (Ripple Carry Out - connects to next stage ENP/ENT)
- Pin 16: VCC
Critical:
- Chain RCO to next stage ENP/ENT for 16-bit counter
- Both ENP and ENT must be HIGH for counting
74HC283 - 4-bit Binary Full Adder (ALU Core)
74HC283
┌──┴──┐
S2 │1 16│ VCC
B2 │2 15│ B3
A2 │3 14│ A3
S1 │4 13│ S3
A1 │5 12│ A4
B1 │6 11│ B4
C0 │7 10│ S4
GND │8 9│ C4
└─────┘
Pin Assignments:
- Pin 1,4,13,10: Sum outputs S1-S4
- Pins 2,6,11,15: B inputs B1-B4
- Pins 3,5,12,14: A inputs A1-A4
- Pin 7: C0 (Carry In)
- Pin 8: GND
- Pin 9: C4 (Carry Out)
- Pin 16: VCC
Critical:
- Chain C4 to next stage C0 for 16-bit addition
- Keep propagation delay in mind: ~25ns typical
74HC157 - Quad 2-Input Multiplexer (ALU Data Paths)
74HC157
┌──┴──┐
SELECT │1 16│ VCC
1A │2 15│ /ENABLE
1B │3 14│ 4A
1Y │4 13│ 4B
2A │5 12│ 4Y
2B │6 11│ 3A
2Y │7 10│ 3B
GND │8 9│ 3Y
└─────┘
Pin Assignments:
- Pin 1: SELECT (0 = A inputs, 1 = B inputs)
- Pins 2,5,11,14: A inputs (1A, 2A, 3A, 4A)
- Pins 3,6,10,13: B inputs (1B, 2B, 3B, 4B)
- Pins 4,7,9,12: Y outputs (1Y, 2Y, 3Y, 4Y)
- Pin 8: GND
- Pin 15: /ENABLE (active LOW, tie to GND)
- Pin 16: VCC
Critical:
- All 4 muxes share same SELECT line
- Can cascade multiple ICs with same SELECT
74HC86 - Quad 2-Input XOR Gate (ALU Negation)
74HC86
┌──┴──┐
1A │1 14│ VCC
1B │2 13│ 4A
1Y │3 12│ 4B
2A │4 11│ 4Y
2B │5 10│ 3A
2Y │6 9│ 3B
GND │7 8│ 3Y
└─────┘
Pin Assignments:
- Pins 1,4,10,13: A inputs
- Pins 2,5,9,12: B inputs
- Pins 3,6,8,11: Y outputs (A XOR B)
- Pin 7: GND
- Pin 14: VCC
Usage for negation:
- Connect data to A inputs
- Connect negate control to ALL B inputs
- When B=0: Y=A (pass through)
- When B=1: Y=/A (invert)
74HC245 - Octal Bus Transceiver (Bus Interface)
74HC245
┌──┴──┐
DIR │1 20│ VCC
A1 │2 19│ A8
A2 │3 18│ A7
A3 │4 17│ A6
A4 │5 16│ A5
A5 │6 15│ A4
A6 │7 14│ A3
A7 │8 13│ A2
A8 │9 12│ A1
GND │10 11│ /OE
└─────┘
Wait, I need to correct this - the 74HC245 has B-side pins too:
74HC245
┌──┴──┐
DIR │1 20│ VCC
A1 │2 19│ B1
A2 │3 18│ B2
A3 │4 17│ B3
A4 │5 16│ B4
A5 │6 15│ B5
A6 │7 14│ B6
A7 │8 13│ B7
A8 │9 12│ B8
GND │10 11│ /OE
└─────┘
Pin Assignments:
- Pin 1: DIR (Direction: 0=B→A, 1=A→B)
- Pins 2-9: A-side data bus A1-A8
- Pin 10: GND
- Pin 11: /OE (Output Enable, active LOW)
- Pins 12-19: B-side data bus B8-B1
- Pin 20: VCC
Critical:
- Use for bidirectional buses
- /OE must be LOW for operation
- DIR controls data flow direction
74HC138 - 3-to-8 Line Decoder (Address Decode)
74HC138
┌──┴──┐
A │1 16│ VCC
B │2 15│ Y0
C │3 14│ Y1
/E1 │4 13│ Y2
/E2 │5 12│ Y3
E3 │6 11│ Y4
Y7 │7 10│ Y5
GND │8 9│ Y6
└─────┘
Pin Assignments:
- Pins 1-3: Address inputs A,B,C
- Pins 4-5: Enable inputs /E1, /E2 (active LOW)
- Pin 6: Enable input E3 (active HIGH)
- Pin 8: GND
- Pins 7,9,10,11,12,13,14,15: Outputs Y7-Y0
- Pin 16: VCC
Enable condition: /E1=0 AND /E2=0 AND E3=1
When enabled, only one output is LOW based on ABC
AS6C4008 - 512Kx8 SRAM (Data Memory)
AS6C4008 (32-pin DIP)
┌──┴──┐
A18 │1 32│ VCC
A16 │2 31│ A17
A15 │3 30│ A14
A12 │4 29│ A13
A7 │5 28│ A8
A6 │6 27│ A9
A5 │7 26│ A11
A4 │8 25│ /OE
A3 │9 24│ A10
A2 │10 23│ /CE
A1 │11 22│ D7
A0 │12 21│ D6
D0 │13 20│ D5
D1 │14 19│ D4
D2 │15 18│ D3
GND │16 17│ /WE
└─────┘
Pin Assignments:
- Pins 1-3,5-12,24,28-31: Address inputs A0-A18
- Pins 13-15,18-22: Data I/O D0-D7
- Pin 16: GND
- Pin 17: /WE (Write Enable, active LOW)
- Pin 23: /CE (Chip Enable, active LOW)
- Pin 25: /OE (Output Enable, active LOW)
- Pin 32: VCC
Critical:
- For Hack: A15-A18 tied to GND (only need 32K)
- Read cycle: /CE=0, /OE=0, /WE=1
- Write cycle: /CE=0, /WE=0, /OE=1
AT28C256 - 32Kx8 EEPROM (Instruction Memory)
AT28C256 (28-pin DIP)
┌──┴──┐
A14 │1 28│ VCC
A12 │2 27│ /WE
A7 │3 26│ A13
A6 │4 25│ A8
A5 │5 24│ A9
A4 │6 23│ A11
A3 │7 22│ /OE
A2 │8 21│ A10
A1 │9 20│ /CE
A0 │10 19│ D7
D0 │11 18│ D6
D1 │12 17│ D5
D2 │13 16│ D4
GND │14 15│ D3
└─────┘
Pin Assignments:
- Pins 1-2,4-10,21,23-26: Address inputs A0-A14
- Pins 11-13,15-19: Data I/O D0-D7
- Pin 14: GND
- Pin 20: /CE (Chip Enable, active LOW)
- Pin 22: /OE (Output Enable, active LOW)
- Pin 27: /WE (Write Enable, active LOW)
- Pin 28: VCC
For read-only ROM:
- /CE = GND (always enabled)
- /OE = GND (always outputting)
- /WE = VCC (never writing)
2. ALU Module PCB Layout
ALU Schematic - 4-bit Slice (Repeat 4x for 16 bits)
X Input Processing:
X[3:0] ────────┬─────────────┐
│ │
┌────▼────┐ ┌────▼────┐
GND─►│2 15/OE│ │2 15/OE│◄─GND
│ 1A 1Y │ │ 1A 1Y │
X[0]───►│5 4 ├─┼───►│5 4 ├────► X_proc[0]
GND────►│3 │ │ │3 │
│ 2A 2Y │ │ │ 2A 2Y │
X[1]───►│6 7 ├─┼───►│6 7 ├────► X_proc[1]
GND────►│11 │ │ │11 │
│ 3A 3Y │ │ │ 3A 3Y │
X[2]───►│14 9 ├─┼───►│14 9 ├────► X_proc[2]
GND────►│13 │ │ │13 │
│ 4A 4Y │ │ │ 4A 4Y │
X[3]───►│10 12 ├─┼───►│10 12 ├────► X_proc[3]
│ │ │ │ │
zx─►│1 SEL │ │nx─►│1,2, │
│ │ │ │10,13 │
└─────┬─┘ │ └───────┘
│ │
GND GND
74HC157 74HC86
MUX #1 XOR #1
Y Input Processing: (identical circuit)
Addition/AND Function:
X_proc[3:0]──┬─────────────┐
│ │
┌────▼────┐ ┌────▼────┐
│3 A1 S1│ │1 1A │
│ 4 ├───┤ │
│5 A2 S2│ │4 1Y │
Y_proc─►│ 1 ├───┤ │
[0] │6 B1 │ │5 2A │
│ │ │ │
Y_proc─►│2 B2 │ │7 2Y ├──┐
[1] │ │ │ │ │
│12 A3 S3│ │11 3A │ │
│ 13 ├───┤ │ │ f select
X_proc─►│14 A4 S4│ │14 3Y │ │ (0=AND,
[2] │ 10 ├───┤ │ │ 1=ADD)
│11 B3 │ │10 4A │ │
Y_proc─►│ │ │ │ │
[2] │15 B4 │ │13 4B │ │
│ │ │ │ │
Y_proc─►│ 7 C0 │ │12 4Y ├──┤
[3] │ 9 C4 ─┼──►next stage│ │
└─────────┘ └─────────┘ │
74HC283 74HC08 │
ADDER AND │
│
┌───────────┐ │
SUM[3:0]───────►│2,5,11,14 │◄──┘
│ A inputs │
AND[3:0]───────►│3,6,10,13 │
│ B inputs │
│ │
f_select───────►│1 SELECT │
│ │
GND────────────►│15 /ENABLE│
│ │
F_out[0]◄─┤4 1Y │
F_out[1]◄─┤7 2Y │
F_out[2]◄─┤9 3Y │
F_out[3]◄─┤12 4Y │
└───────────┘
74HC157 MUX
Output Negation:
F_out[3:0] ────────┬───────────┐
│ │
┌────▼────┐ │
no────►│1,2, │ │
control │10,13 │ │
│ │ │
F_out[0]─►│4 3 XOR├─────► ALU_out[0]
F_out[1]─►│5 6 XOR├─────► ALU_out[1]
F_out[2]─►│9 8 XOR├─────► ALU_out[2]
F_out[3]─►│10 11XOR├─────► ALU_out[3]
│ │
└─────────┘
74HC86 XOR
ALU PCB Layout (Top View)
┌──────────────────────────────────────────────────────────┐
│ ALU MODULE - 4 slices (16-bit complete) │
│ │
│ INPUT CONDITIONING SECTION │
│ ┌──────────────────────────────────────────────────┐ │
│ │ Slice 0 [3:0] Slice 1 [7:4] │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U1│ │U5│ │U9│ │U13│ X-input MUX (zx) │ │
│ │ └──┘ └──┘ └──┘ └──┘ 74HC157 x4 │ │
│ │ │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U2│ │U6│ │U10│ │U14│ X-input XOR (nx) │ │
│ │ └──┘ └──┘ └──┘ └──┘ 74HC86 x4 │ │
│ │ │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U3│ │U7│ │U11│ │U15│ Y-input MUX (zy) │ │
│ │ └──┘ └──┘ └──┘ └──┘ 74HC157 x4 │ │
│ │ │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U4│ │U8│ │U12│ │U16│ Y-input XOR (ny) │ │
│ │ └──┘ └──┘ └──┘ └──┘ 74HC86 x4 │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ FUNCTION EXECUTION SECTION │
│ ┌──────────────────────────────────────────────────┐ │
│ │ Slice 0 Slice 1 Slice 2 Slice 3 │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U17│────C4───►U18│────C4────►U19│─────►U20│ │ │
│ │ └──┘ (carry) └──┘ (carry) └──┘ └──┘ │ │
│ │ 74HC283 ADDER CHAIN (4-bit each) │ │
│ │ │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U21│ │U22│ │U23│ │U24│ │ │
│ │ └──┘ └──┘ └──┘ └──┘ │ │
│ │ 74HC08 AND GATES (4-bit each) │ │
│ │ │ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U25│ │U26│ │U27│ │U28│ │ │
│ │ └──┘ └──┘ └──┘ └──┘ │ │
│ │ 74HC157 FUNC SELECT MUX (f control) │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ OUTPUT NEGATION SECTION │
│ ┌──────────────────────────────────────────────────┐ │
│ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │
│ │ │U29│ │U30│ │U31│ │U32│ │ │
│ │ └──┘ └──┘ └──┘ └──┘ │ │
│ │ 74HC86 OUTPUT XOR (no control) │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ STATUS FLAGS │
│ ┌──────────────────────────────────────────────────┐ │
│ │ ┌──┐ ┌──┐ │ │
│ │ │U33│ │U34│ Zero detect (NOR gates) │ │
│ │ └──┘ └──┘ 74HC4078 (8-input NOR) + combine │ │
│ │ │ │
│ │ ng = ALU_out[15] (MSB is sign bit) │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ CONNECTORS │
│ [J1: X_in 16-bit] [J2: Y_in 16-bit] [J3: Control 6-bit]│
│ [J4: ALU_out 16-bit] [J5: Flags (zr,ng)] │
└──────────────────────────────────────────────────────────┘
Board size: 6" x 8"
Layer count: 4 layers recommended
ALU Critical Traces
PRIORITY 1 - Control Signals (shared by many ICs):
┌─────────────────────────────────────────┐
│ zx ──────────────────────────────┐ │
│ │ │
│ ├─► U1:pin1 │ │
│ ├─► U9:pin1 (Star topology) │ │
│ ├─► ...all X-muxes │ │
│ │ │
│ Trace: 15 mil width │ │
│ Keep star point central │ │
│ Max stub length: 1 inch │ │
└─────────────────────────────────────────┘
PRIORITY 2 - Carry Chain (timing critical):
┌─────────────────────────────────────────┐
│ U17:pin9 (C4)──────► U18:pin7 (C0) │
│ U18:pin9 (C4)──────► U19:pin7 (C0) │
│ U19:pin9 (C4)──────► U20:pin7 (C0) │
│ │
│ Trace: 10 mil width │
│ Keep straight, minimize length │
│ No vias if possible │
│ Match lengths within 50 mil │
└─────────────────────────────────────────┘
PRIORITY 3 - Data Buses:
- Use bus routing (group parallel traces)
- 10 mil width, 10 mil spacing
- Route as differential pairs where possible
3. Register File PCB Layout
A Register Schematic (16-bit using 74HC574)
Pin Connections for A Register:
U1 (74HC574) U2 (74HC574)
Low Byte High Byte
VCC ────► pin 20 pin 20 ◄──── VCC
GND ────► pin 10 pin 10 ◄──── GND
Data In:
D[0] ───► pin 2 D[8] ────► pin 2
D[1] ───► pin 3 D[9] ────► pin 3
D[2] ───► pin 4 D[10] ───► pin 4
D[3] ───► pin 5 D[11] ───► pin 5
D[4] ───► pin 19 D[12] ───► pin 19
D[5] ───► pin 18 D[13] ───► pin 18
D[6] ───► pin 17 D[14] ───► pin 17
D[7] ───► pin 16 D[15] ───► pin 16
Data Out:
Q[0] ◄─── pin 6 Q[8] ◄──── pin 6
Q[1] ◄─── pin 7 Q[9] ◄──── pin 7
Q[2] ◄─── pin 8 Q[10] ◄─── pin 8
Q[3] ◄─── pin 9 Q[11] ◄─── pin 9
Q[4] ◄─── pin 15 Q[12] ◄─── pin 15
Q[5] ◄─── pin 14 Q[13] ◄─── pin 14
Q[6] ◄─── pin 13 Q[14] ◄─── pin 13
Q[7] ◄─── pin 12 Q[15] ◄─── pin 12
Control:
LOAD_A ──┬──► pin 11 (CLK) pin 11 (CLK) ◄──┘
│
GND ─────┼──► pin 1 (/OE) pin 1 (/OE) ◄────┘
│ (always enabled) (always enabled)
Decoupling:
0.1µF cap between pins 20-10 pins 20-10
D Register: Identical to A Register
Program Counter (15-bit using 74HC161)
PC Chain - 4× 74HC161 counters
U1 [3:0] U2 [7:4] U3 [11:8] U4 [14:12]
VCC ───► pin 16 pin 16 pin 16 pin 16
GND ───► pin 8 pin 8 pin 8 pin 8
Clock:
CLK ────┬─► pin 2 pin 2 pin 2 pin 2
│
Parallel Load (from A register):
A[0] ───► pin 3
A[1] ───► pin 4
A[2] ───► pin 5
A[3] ───► pin 6
A[4] ──────────────► pin 3
A[5] ──────────────► pin 4
A[6] ──────────────► pin 5
A[7] ──────────────► pin 6
A[8] ─────────────────────────► pin 3
A[9] ─────────────────────────► pin 4
A[10] ────────────────────────► pin 5
A[11] ────────────────────────► pin 6
A[12] ────────────────────────────────────► pin 3
A[13] ────────────────────────────────────► pin 4
A[14] ────────────────────────────────────► pin 5
GND ──────────────────────────────────────► pin 6
Outputs to ROM Address:
PC[0] ◄── pin 14 PC[4] ◄─ pin 14 PC[8] ◄─ pin 14 PC[12]◄─ pin 14
PC[1] ◄── pin 13 PC[5] ◄─ pin 13 PC[9] ◄─ pin 13 PC[13]◄─ pin 13
PC[2] ◄── pin 12 PC[6] ◄─ pin 12 PC[10]◄─ pin 12 PC[14]◄─ pin 12
PC[3] ◄── pin 11 PC[7] ◄─ pin 11 PC[11]◄─ pin 11 (unused)
Counter Chain (Ripple Carry):
pin 15──► pin 7,10 pin 15─► pin 7,10 pin 15
(RCO) (ENP,ENT) (RCO) (ENP,ENT) (RCO)
Control Logic:
PC_INC ──┬─► pin 7,10 (ENP,ENT on U1)
│
PC_LOAD ─┴─► pin 9 (inverted, to /LOAD on all)
RESET ───┬─► pin 1 (/CLR on all counters)
Additional Logic for PC Control (using 74HC00):
74HC00 (U5)
┌──┴──┐
JUMP ───►│1 3├──┬─► PC_LOAD (goes to all /LOAD pins)
JUMP ───►│2 │ │
│ │ │
/JUMP ──►│4 6├──┴─► PC_INC (goes to ENP/ENT of U1)
/RESET ─►│5 │
└─────┘
Register File PCB Layout
┌────────────────────────────────────────────────────┐
│ REGISTER FILE MODULE │
│ │
│ A REGISTER (16-bit) │
│ ┌──────────────────────────────────┐ │
│ │ ┌────┐ ┌────┐ │ │
│ │ │ U1 │ [7:0] │ U2 │ [15:8]│ │
│ │ │574 │ │574 │ │ │
│ │ └────┘ └────┘ │ │
│ │ 74HC574 × 2 │ │
│ │ │ │
│ │ J1: Data_In[15:0] │ │
│ │ J2: A_Out[15:0] │ │
│ │ J3: LOAD_A (clock) │ │
│ └──────────────────────────────────┘ │
│ │
│ D REGISTER (16-bit) │
│ ┌──────────────────────────────────┐ │
│ │ ┌────┐ ┌────┐ │ │
│ │ │ U3 │ [7:0] │ U4 │ [15:8]│ │
│ │ │574 │ │574 │ │ │
│ │ └────┘ └────┘ │ │
│ │ 74HC574 × 2 │ │
│ │ │ │
│ │ J4: Data_In[15:0] │ │
│ │ J5: D_Out[15:0] │ │
│ │ J6: LOAD_D (clock) │ │
│ └──────────────────────────────────┘ │
│ │
│ PROGRAM COUNTER (15-bit) │
│ ┌──────────────────────────────────────────────┐ │
│ │ ┌────┐ ┌────┐ ┌────┐ ┌────┐ │ │
│ │ │ U6 │ │ U7 │ │ U8 │ │ U9 │ │ │
│ │ │161 │─►│161 │─►│161 │─►│161 │ │ │
│ │ └────┘ └────┘ └────┘ └────┘ │ │
│ │ [3:0] [7:4] [11:8] [14:12] │ │
│ │ 74HC161 × 4 (chained) │ │
│ │ │ │
│ │ ┌────┐ │ │
│ │ │U10 │ PC Control Logic │ │
│ │ │00 │ 74HC00 │ │
│ │ └────┘ │ │
│ │ │ │
│ │ J7: A_In[14:0] (parallel load) │ │
│ │ J8: PC_Out[14:0] (to ROM address) │ │
│ │ J9: Control (JUMP, RESET, CLK) │ │
│ └──────────────────────────────────────────────┘ │
│ │
│ Power Distribution: │
│ [VCC bus] ─────────────┬────────────────── │
│ │ │
│ [GND bus] ─────────────┴────────────────── │
│ │
│ Decoupling: 0.1µF cap at each IC (VCC-GND) │
│ Bulk: 10µF tantalum at power entry │
└────────────────────────────────────────────────────┘
Board size: 4" × 6"
4. Memory Module PCB Layout
ROM Interface (Instruction Memory)
ROM Schematic - 2× AT28C256 for 16-bit instructions
AT28C256 (U1) AT28C256 (U2)
Low Byte [7:0] High Byte [15:8]
Address (shared):
PC[0] ──┬─► pin 10 (A0) pin 10 (A0)
PC[1] ──┼─► pin 9 (A1) pin 9 (A1)
PC[2] ──┼─► pin 8 (A2) pin 8 (A2)
PC[3] ──┼─► pin 7 (A3) pin 7 (A3)
PC[4] ──┼─► pin 6 (A4) pin 6 (A4)
PC[5] ──┼─► pin 5 (A5) pin 5 (A5)
PC[6] ──┼─► pin 4 (A6) pin 4 (A6)
PC[7] ──┼─► pin 3 (A7) pin 3 (A7)
PC[8] ──┼─► pin 25 (A8) pin 25 (A8)
PC[9] ──┼─► pin 24 (A9) pin 24 (A9)
PC[10] ─┼─► pin 21 (A10) pin 21 (A10)
PC[11] ─┼─► pin 23 (A11) pin 23 (A11)
PC[12] ─┼─► pin 2 (A12) pin 2 (A12)
PC[13] ─┼─► pin 26 (A13) pin 26 (A13)
PC[14] ─┴─► pin 1 (A14) pin 1 (A14)
Data Out:
Inst[0] ◄── pin 11 (D0)
Inst[1] ◄── pin 12 (D1)
Inst[2] ◄── pin 13 (D2)
Inst[3] ◄── pin 15 (D3)
Inst[4] ◄── pin 16 (D4)
Inst[5] ◄── pin 17 (D5)
Inst[6] ◄── pin 18 (D6)
Inst[7] ◄── pin 19 (D7)
Inst[8] ◄── pin 11 (D0)
Inst[9] ◄── pin 12 (D1)
Inst[10]◄── pin 13 (D2)
Inst[11]◄── pin 15 (D3)
Inst[12]◄── pin 16 (D4)
Inst[13]◄── pin 17 (D5)
Inst[14]◄── pin 18 (D6)
Inst[15]◄── pin 19 (D7)
Control (both chips):
GND ────┬─► pin 20 (/CE - always enabled)
│ pin 22 (/OE - always enabled)
│
VCC ────┴─► pin 27 (/WE - never write)
Power:
VCC ────┬─► pin 28
│
GND ────┴─► pin 14
RAM Interface (Data Memory)
RAM Schematic - 2× AS6C4008 for 16-bit data
AS6C4008 (U3) AS6C4008 (U4)
Low Byte [7:0] High Byte [15:8]
Address (from A register):
A[0] ───┬─► pin 12 (A0) pin 12 (A0)
A[1] ───┼─► pin 11 (A1) pin 11 (A1)
A[2] ───┼─► pin 10 (A2) pin 10 (A2)
A[3] ───┼─► pin 9 (A3) pin 9 (A3)
A[4] ───┼─► pin 8 (A4) pin 8 (A4)
A[5] ───┼─► pin 7 (A5) pin 7 (A5)
A[6] ───┼─► pin 6 (A6) pin 6 (A6)
A[7] ───┼─► pin 5 (A7) pin 5 (A7)
A[8] ───┼─► pin 28 (A8) pin 28 (A8)
A[9] ───┼─► pin 27 (A9) pin 27 (A9)
A[10] ──┼─► pin 24 (A10) pin 24 (A10)
A[11] ──┼─► pin 26 (A11) pin 26 (A11)
A[12] ──┼─► pin 4 (A12) pin 4 (A12)
A[13] ──┼─► pin 29 (A13) pin 29 (A13)
A[14] ──┴─► pin 3 (A14) pin 3 (A14)
Data (bidirectional via 74HC245):
Connect through bus transceivers (see below)
Control:
GND ────┬─► pin 23 (/CE - always enabled)
│
READ_M ─┼─► pin 25 (/OE - active LOW)
│
WRITE_M┴─► pin 17 (/WE - active LOW)
Power:
VCC ────┬─► pin 32
│
GND ────┴─► pin 16
Unused address lines:
GND ────┬─► pin 2 (A16)
├─► pin 31 (A17)
└─► pin 1 (A18)
Bus Transceiver for RAM (74HC245)
RAM Data Bus Interface - 2× 74HC245
74HC245 (U5) 74HC245 (U6)
Low Byte High Byte
CPU Bus:
DB[0] ◄─► pin 2 (A1) ◄─► pin 19 (B1) ◄─► RAM_D[0]
DB[1] ◄─► pin 3 (A2) ◄─► pin 18 (B2) ◄─► RAM_D[1]
DB[2] ◄─► pin 4 (A3) ◄─► pin 17 (B3) ◄─► RAM_D[2]
DB[3] ◄─► pin 5 (A4) ◄─► pin 16 (B4) ◄─► RAM_D[3]
DB[4] ◄─► pin 6 (A5) ◄─► pin 15 (B5) ◄─► RAM_D[4]
DB[5] ◄─► pin 7 (A6) ◄─► pin 14 (B6) ◄─► RAM_D[5]
DB[6] ◄─► pin 8 (A7) ◄─► pin 13 (B7) ◄─► RAM_D[6]
DB[7] ◄─► pin 9 (A8) ◄─► pin 12 (B8) ◄─► RAM_D[7]
DB[8] ◄─► pin 2 ◄─► pin 19 ◄─► RAM_D[8]
...similar for DB[9:15]
Control:
WRITE_M ─┬─► pin 1 (DIR) 0=B→A (read), 1=A→B (write)
│
GND ─────┴─► pin 11 (/OE) Always enabled
Memory Module PCB Layout
┌──────────────────────────────────────────────────────────┐
│ MEMORY MODULE │
│ │
│ INSTRUCTION ROM (Read-Only) │
│ ┌──────────────────────────────────────────────────┐ │
│ │ │ │
│ │ ┌─────────┐ ┌─────────┐ │ │
│ │ │ U1 │ │ U2 │ │ │
│ │ │AT28C256 │ │AT28C256 │ │ │
│ │ │ [7:0] │ │ [15:8] │ │ │
│ │ └─────────┘ └─────────┘ │ │
│ │ │ │
│ │ Address Bus: PC[14:0] ─────────────────────► │ │
│ │ Data Out: Instruction[15:0] ────────────────► │ │
│ │ │ │
│ │ ZIF Sockets recommended for easy programming │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ DATA RAM (Read/Write) │
│ ┌──────────────────────────────────────────────────┐ │
│ │ │ │
│ │ ┌─────────┐ ┌─────────┐ │ │
│ │ │ U3 │ │ U4 │ │ │
│ │ │AS6C4008 │ │AS6C4008 │ │ │
│ │ │ [7:0] │ │ [15:8] │ │ │
│ │ └─────────┘ └─────────┘ │ │
│ │ │ │ │ │
│ │ └────────┬───────────────┘ │ │
│ │ │ │ │
│ │ ┌─────────┐ │ ┌─────────┐ │ │
│ │ │ U5 │◄─┴─►│ U6 │ │ │
│ │ │ 74HC245 │ │ 74HC245 │ │ │
│ │ │ [7:0] │ │ [15:8] │ │ │
│ │ └─────────┘ └─────────┘ │ │
│ │ │ │ │ │
│ │ └────────┬───────┘ │ │
│ │ ▼ │ │
│ │ CPU Data Bus │ │
│ │ │ │
│ │ Address Bus: A[14:0] ──────────────────────► │ │
│ │ Control: READ_M, WRITE_M ──────────────────► │ │
│ └──────────────────────────────────────────────────┘ │
│ │
│ CONNECTORS │
│ ┌────────────────────────────────────────────────┐ │
│ │ J1: PC[14:0] (from Program Counter) │ │
│ │ J2: Instruction[15:0] (to Control Unit) │ │
│ │ J3: A[14:0] (from A Register) │ │
│ │ J4: Data Bus[15:0] (bidirectional) │ │
│ │ J5: Control (READ_M, WRITE_M) │ │
│ │ J6: Power (+5V, GND) │ │
│ └────────────────────────────────────────────────┘ │
│ │
│ POWER │
│ • Bulk caps: 100µF @ power entry │
│ • Bypass: 0.1µF at each IC │
│ • Estimated current: 500mA │
└──────────────────────────────────────────────────────────┘
Board size: 5" × 6"
Layer count: 2 layers sufficient (address bus on one layer,
data bus on other)
5. Control Unit PCB Layout
Instruction Decoder Schematic
Complete Control Unit using 74HC logic:
INSTRUCTION TYPE DETECTOR:
┌────────┐
Inst[15] ──────►│1 2 │
│ 74HC04├────► C_INST (1 = C-instruction)
│ │
└────────┘
DESTINATION DECODER (for C-instructions):
┌─────────┐
Inst[5] ───►│1 3 ├──┬──► destA_raw
C_INST ────►│2 74HC08│ │
└─────────┘ │
│ ┌─────────┐
└────►│1 3 ├─► LOAD_A
/C_INST (A-inst) ──────────────►│2 74HC32│
└─────────┘
(A-instruction also loads A register)
┌─────────┐
Inst[4] ───►│1 3 ├──► LOAD_D
C_INST ────►│2 74HC08│
└─────────┘
┌─────────┐
Inst[3] ───►│1 3 ├──► WRITE_M
C_INST ────►│2 74HC08│
└─────────┘
ALU CONTROL (direct from instruction):
Inst[11] ────────────────────► zx (ALU control bit 5)
Inst[10] ────────────────────► nx (ALU control bit 4)
Inst[9] ─────────────────────► zy (ALU control bit 3)
Inst[8] ─────────────────────► ny (ALU control bit 2)
Inst[7] ─────────────────────► f (ALU control bit 1)
Inst[6] ─────────────────────► no (ALU control bit 0)
A/M SELECT:
Inst[12] ────────────────────► A_OR_M (0=A, 1=M[A])
JUMP LOGIC (using 74HC151 8:1 MUX):
74HC151 (U7)
┌──┴──┐
Inst[0] ─►│11 A │ Select inputs (jjj bits)
Inst[1] ─►│10 B │
Inst[2] ─►│9 C │
│ │
GND ───►│7 /E │ Enable (active LOW)
│ │
Data inputs (based on ALU flags):
GND ─────►│4 D0│ j=000: never jump
│ │
out_pos ─►│3 D1│ j=001: JGT (out > 0)
zr ──────►│2 D2│ j=010: JEQ (out == 0)
out_geq ─►│1 D3│ j=011: JGE (out >= 0)
ng ──────►│15 D4│ j=100: JLT (out < 0)
out_neq ─►│14 D5│ j=101: JNE (out != 0)
out_leq ─►│13 D6│ j=110: JLE (out <= 0)
VCC ─────►│12 D7│ j=111: JMP (always)
│ │
PC_LOAD ◄─┤5 Y │ Mux output
└─────┘
Supporting logic for jump conditions (74HC00, 74HC02, 74HC32):
out_pos = /zr AND /ng (positive: not zero, not negative)
out_geq = /ng (greater or equal: not negative)
out_neq = /zr (not equal: not zero)
out_leq = zr OR ng (less or equal: zero or negative)
┌─────────┐
/zr ─────►│1 3 ├──► out_pos
/ng ─────►│2 74HC08│
└─────────┘
/ng ─────────────────────► out_geq
/zr ─────────────────────► out_neq
┌─────────┐
zr ─────►│1 3 ├──► out_leq
ng ─────►│2 74HC32│
└─────────┘
PC INCREMENT LOGIC:
┌─────────┐
PC_LOAD ───►│1 3 ├──► /PC_INC
PC_LOAD ───►│2 74HC00│
└─────────┘
(PC increments when not loading/jumping)
Control Unit PCB Layout
┌───────────────────────────────────────────────────────────┐
│ CONTROL UNIT MODULE │
│ │
│ INSTRUCTION DECODE SECTION │
│ ┌────────────────────────────────────────────────────┐ │
│ │ │ │
│ │ ┌────┐ │ │
│ │ │ U1 │ Type Detector (C-inst vs A-inst) │ │
│ │ │'04 │ 74HC04 │ │
│ │ └────┘ │ │
│ │ │ │
│ │ ┌────┐ ┌────┐ ┌────┐ │ │
│ │ │ U2 │ │ U3 │ │ U4 │ Destination Decoders │ │
│ │ │'08 │ │'08 │ │'32 │ 74HC08 / 74HC32 │ │
│ │ └────┘ └────┘ └────┘ │ │
│ │ │ │
│ │ Outputs: LOAD_A, LOAD_D, WRITE_M │ │
│ └────────────────────────────────────────────────────┘ │
│ │
│ ALU CONTROL (Direct routing) │
│ ┌────────────────────────────────────────────────────┐ │
│ │ Inst[11:6] ──────────► ALU_CTRL[5:0] │ │
│ │ (zx,nx,zy,ny,f,no) │ │
│ │ │ │
│ │ Inst[12] ────────────► A_OR_M │ │
│ └────────────────────────────────────────────────────┘ │
│ │
│ JUMP LOGIC SECTION │
│ ┌────────────────────────────────────────────────────┐ │
│ │ │ │
│ │ ┌────┐ ┌────┐ ┌────┐ │ │
│ │ │ U5 │ │ U6 │ │ U7 │ Condition Generators │ │
│ │ │'08 │ │'32 │ │'00 │ 74HC08/32/00 │ │
│ │ └────┘ └────┘ └────┘ │ │
│ │ │ │
│ │ Generates: out_pos, out_geq, out_neq, out_leq │ │
│ │ │ │
│ │ │ │
│ │ ┌─────────┐ │ │
│ │ │ U8 │ Jump Multiplexer │ │
│ │ │ 74HC151 │ 8:1 MUX │ │
│ │ │ │ Selects jump based on jjj bits │ │
│ │ └─────────┘ │ │
│ │ │ │ │
│ │ └──────────► PC_LOAD │ │
│ │ │ │
│ │ ┌────┐ │ │
│ │ │ U9 │ PC Increment Logic │ │
│ │ │'00 │ 74HC00 │ │
│ │ └────┘ │ │
│ │ │ │ │
│ │ └──────────► PC_INC │ │
│ └────────────────────────────────────────────────────┘ │
│ │
│ CONNECTORS │
│ ┌────────────────────────────────────────────────────┐ │
│ │ J1: Instruction[15:0] (from ROM) │ │
│ │ J2: ALU_CTRL[5:0] (to ALU) │ │
│ │ J3: Register Controls (LOAD_A, LOAD_D) │ │
│ │ J4: Memory Controls (WRITE_M, READ_M) │ │
│ │ J5: PC Controls (PC_LOAD, PC_INC) │ │
│ │ J6: ALU Flags (zr, ng from ALU) │ │
│ │ J7: Misc Signals (A_OR_M, C_INST) │ │
│ │ J8: Power (+5V, GND) │ │
│ └────────────────────────────────────────────────────┘ │
│ │
│ LED DEBUG INDICATORS │
│ ┌────────────────────────────────────────────────────┐ │
│ │ [LED] C_INST [LED] LOAD_A [LED] LOAD_D │ │
│ │ [LED] WRITE_M [LED] PC_LOAD [LED] PC_INC │ │
│ │ │ │
│ │ Each LED: 330Ω resistor in series │ │
│ └────────────────────────────────────────────────────┘ │
└───────────────────────────────────────────────────────────┘
Board size: 4" × 5"
Layer count: 2 layers
6. Main Board Integration
Complete System Interconnection
┌──────────────────────────────────────────────────────────────┐
│ HACK COMPUTER MAIN BOARD │
│ (Top View) │
│ │
│ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ │
│ │ POWER │ │ CLOCK │ │ RESET │ │
│ │ SUPPLY │ │ GENERATOR │ │ CIRCUIT │ │
│ │ SECTION │ │ │ │ │ │
│ │ │ │ ┌────┐ │ │ ┌────┐ │ │
│ │ 7805 or LDO │ │ │555 │ │ │ │Push│ │ │
│ │ +5V @ 2A │ │ └────┘ │ │ │Btn │ │ │
│ │ │ │ │ │ └────┘ │ │
│ │ [PWR LED] │ │ [CLK LED] │ │ [RST LED] │ │
│ └──────────────┘ └──────────────┘ └──────────────┘ │
│ │
│ ┌─────────────────────────────────────────────────────────┐ │
│ │ DATA PATH SECTION │ │
│ │ │ │
│ │ ┌──────────────────────────────────────────────────┐ │ │
│ │ │ ALU MODULE (6"×8" board) │ │ │
│ │ │ 32 ICs: Input conditioning, ADD/AND, Output │ │ │
│ │ │ │ │ │
│ │ │ Inputs: X[15:0], Y[15:0], CTRL[5:0] │ │ │
│ │ │ Outputs: Result[15:0], zr, ng │ │ │
│ │ └──────────────────────────────────────────────────┘ │ │
│ │ ▲ │ │ │
│ │ │ ▼ │ │
│ │ ┌───────┴────────┐ ┌──────────────────┐ │ │
│ │ │ REGISTER FILE │ │ BUS INTERFACE │ │ │
│ │ │ (4"×6" bd) │ │ │ │ │
│ │ │ │ │ 4× 74HC245 │ │ │
│ │ │ A Reg (2×574) │ │ Transceivers │ │ │
│ │ │ D Reg (2×574) │ │ │ │ │
│ │ │ PC (4×161) │ └──────────────────┘ │ │
│ │ └────────────────┘ │ │
│ └─────────────────────────────────────────────────────────┘ │
│ │
│ ┌─────────────────────────────────────────────────────────┐ │
│ │ MEMORY SECTION │ │
│ │ │ │
│ │ ┌────────────────────┐ ┌────────────────────┐ │ │
│ │ │ INSTRUCTION ROM │ │ DATA RAM │ │ │
│ │ │ (5"×6" board) │ │ (5"×6" board) │ │ │
│ │ │ │ │ │ │ │
│ │ │ 2× AT28C256 EEPROM │ │ 2× AS6C4008 SRAM │ │ │
│ │ │ [Inst 15:0 out] │ │ 2× 74HC245 I/F │ │ │
│ │ │ │ │ │ │ │
│ │ └────────────────────┘ └────────────────────┘ │ │
│ │ ▲ ▲ │ │
│ │ │ │ │ │
│ │ PC[14:0] A[14:0] │ │
│ └─────────────────────────────────────────────────────────┘ │
│ │
│ ┌─────────────────────────────────────────────────────────┐ │
│ │ CONTROL SECTION │ │
│ │ │ │
│ │ ┌──────────────────────────────────────────────────┐ │ │
│ │ │ CONTROL UNIT (4"×5" board) │ │ │
│ │ │ │ │ │
│ │ │ Instruction Decoder + Jump Logic │ │ │
│ │ │ ~10 ICs (74HC00/02/04/08/32/151) │ │ │
│ │ │ │ │ │
│ │ │ Inputs: Inst[15:0], zr, ng │ │ │
│ │ │ Outputs: ALU_CTRL, LOAD_A/D, WRITE_M, │ │ │
│ │ │ PC_LOAD, PC_INC, A_OR_M │ │ │
│ │ └──────────────────────────────────────────────────┘ │ │
│ └─────────────────────────────────────────────────────────┘ │
│ │
│ ┌─────────────────────────────────────────────────────────┐ │
│ │ DEBUG SECTION │ │
│ │ │ │
│ │ [16× LEDs for Data Bus] [8× LEDs for Status] │ │
│ │ [DIP Switches for Manual Input] │ │
│ │ [Single-Step Button] [Run/Halt Switch] │ │
│ │ [7-Segment Displays for PC, A, D] │ │
│ │ [Logic Analyzer Headers] │ │
│ └─────────────────────────────────────────────────────────┘ │
│ │
│ EXPANSION CONNECTORS (Bottom Edge) │
│ [UART] [VGA] [PS/2] [SD Card] [GPIO] │
└──────────────────────────────────────────────────────────────┘
Main Board Size: 14" × 12" (or use backplane with daughter cards)
Total IC Count: ~75-80 ICs
Power: +5V @ 2A
7. Critical Routing Guidelines
Layer Stack-Up (4-layer board recommended)
┌────────────────────────────────────┐
│ Layer 1: TOP (Component Side) │
│ - Signal routing │
│ - Component pads │
│ - Horizontal traces preferred │
│ - 10 mil minimum width │
└────────────────────────────────────┘
┌────────────────────────────────────┐
│ Layer 2: GROUND PLANE │
│ - Solid copper pour │
│ - Vias for all GND connections │
│ - Cut-outs only where necessary │
└────────────────────────────────────┘
┌────────────────────────────────────┐
│ Layer 3: POWER PLANE (+5V) │
│ - Solid copper pour │
│ - Vias for all VCC connections │
│ - Cut-outs for signal vias │
└────────────────────────────────────┘
┌────────────────────────────────────┐
│ Layer 4: BOTTOM (Secondary Side) │
│ - Signal routing │
│ - Vertical traces preferred │
│ - Additional components if needed │
│ - 10 mil minimum width │
└────────────────────────────────────┘
Via Specifications:
- Pad diameter: 24 mil
- Drill: 12 mil
- Minimum annular ring: 6 mil
Trace Width Guidelines
Signal Type | Width | Spacing | Notes
---------------------|--------|---------|----------------------
Power (+5V) | 25 mil | 15 mil | 500mA per trace
Ground | 25 mil | 15 mil | Return paths
Clock (CLK) | 15 mil | 15 mil | Impedance controlled
Data Bus [15:0] | 10 mil | 10 mil | Group routing
Address Bus [14:0] | 10 mil | 10 mil | Group routing
Control Signals | 10 mil | 10 mil | Standard digital
ALU Carry Chain | 12 mil | 12 mil | Timing critical
Bus Routing Strategy
DATA BUS [15:0] Routing:
Layer 1 (Top):
D[0], D[2], D[4], D[6], D[8], D[10], D[12], D[14]
Even-numbered data lines
Layer 4 (Bottom):
D[1], D[3], D[5], D[7], D[9], D[11], D[13], D[15]
Odd-numbered data lines
Keepout zones:
- 50 mil from clock traces
- 30 mil from edge of board
Termination:
- Consider 100Ω series resistors near drivers
- For clock: 33Ω series + 100pF to GND at endpoints
Decoupling Capacitor Placement
Standard Practice:
┌─────────────────────────────────┐
│ 74HC574 (Top View) │
│ │
│ ┌──┐ │
│ │IC│ │
│ └──┘ │
│ │ │ │
│ VCC─┤ └─GND │
│ │ │ │
│ ┌─┴──┴─┐ │
│ │ 0.1µF│ ◄─── Place as close as
│ │ Cap │ possible to pins
│ └──────┘ │
│ │
│ Via to Layer 2 (GND) ───┐ │
│ Via to Layer 3 (VCC) ───┘ │
└─────────────────────────────────┘
Bulk Capacitors:
- 100µF electrolytic every 10 ICs
- 10µF tantalum at power entry
- Place near high-current sections (ALU, RAM)
Clock Distribution
Clock Tree (Star Topology):
555 Timer
│
┌───▼───┐
│74HC04 │ Clock Buffer
│ (×6) │
└───┬───┘
│
┌───────┼───────┬───────┬───────┐
│ │ │ │ │
┌─▼─┐ ┌─▼─┐ ┌─▼─┐ ┌─▼─┐ ┌─▼─┐
│ALU│ │Reg│ │PC │ │Ctl│ │Mem│
└───┘ └───┘ └───┘ └───┘ └───┘
Trace Requirements:
- Maximum length from buffer: 3 inches
- Matched lengths within ±0.5 inch
- No stubs (point-to-point only)
- 50Ω controlled impedance (if >10MHz)
- Series termination: 33Ω near source
Ground Plane Management
Ground Plane Strategy:
┌────────────────────────────────────┐
│ GROUND PLANE (Layer 2) │
│ │
│ ┌─────────────────────────────┐ │
│ │ Digital Section │ │
│ │ (ALU, Registers, Control) │ │
│ │ │ │
│ └─────────────────────────────┘ │
│ │ │
│ Single Point │
│ Connection │
│ │ │
│ ┌────────▼────────────────────┐ │
│ │ Memory Section │ │
│ │ (ROM, RAM, I/O) │ │
│ │ │ │
│ └─────────────────────────────┘ │
│ │
│ Via stitching every 0.5 inch │
│ No cut-outs except for signals │
└────────────────────────────────────┘
8. PCB Design Checklist
Pre-Layout
- Complete schematic with all ICs
- Bill of materials verified
- Footprints for all components
- Pin assignments verified
- Power budget calculated
- Signal integrity analysis
Layout Phase
- Component placement optimized for signal flow
- Critical paths identified and routed first
- Clock distribution implemented
- Power planes continuous
- Ground plane continuous
- Decoupling caps placed correctly
- Via stitching on ground/power planes
- Silkscreen labels clear
- Mounting holes placed
Pre-Fabrication
- DRC (Design Rule Check) passed
- ERC (Electrical Rule Check) passed
- All traces meet width/spacing requirements
- All vias meet size requirements
- Layer stack-up documented
- Gerber files generated
- BOM exported
- Assembly drawings created
Post-Fabrication
- Visual inspection
- Continuity test (all power/ground)
- Short circuit test
- Power-on test (no smoke!)
- Clock signal verification
- Module-by-module testing
This comprehensive guide provides the detailed pinouts and PCB layouts needed to build the Hack computer. Would you like me to expand on any specific section, such as providing KiCad schematic files, gerber generation guidelines, or detailed assembly instructions?